Develop RTL code for digital circuits and systems using Verilog or VHDL, ensuring high performance and low power consumption.

Perform logic synthesis, place and route, and timing analysis to meet design specifications and optimize for area and speed.

Conduct thorough verification and validation of RTL designs through simulation, emulation, and formal verification techniques.

Collaborate with architects and system engineers to define micro-architecture and translate specifications into RTL implementations.

Debug and resolve complex design issues, working closely with verification and physical design teams to ensure robust solutions.

Optimize RTL code for power, performance, and area (PPA) based on simulation results and feedback from physical design teams.

Create and maintain detailed design documentation, including specifications, design descriptions, and verification plans.

Participate in code reviews and provide constructive feedback to improve code quality and adherence to coding standards.

Stay updated with the latest industry trends and advancements in RTL design methodologies and tools.

Develop and implement RTL code using Verilog or VHDL, ensuring high performance and low power consumption.

Create and execute verification plans to validate RTL designs, identifying and fixing bugs early in the design cycle.

Perform synthesis to translate RTL code into gate-level netlists, and conduct timing analysis to meet performance goals.

Implement and test RTL designs on FPGA platforms for early validation and system integration.

Analyze and optimize RTL designs for power efficiency, using techniques like clock gating and power domain partitioning.

Create comprehensive documentation for RTL designs, including specifications, design details, and verification reports.

Work closely with architects, verification engineers, and physical design teams, participating in design reviews.

Debug and identify root causes of design issues, implementing effective solutions and preventive measures.