Conduct DFT architecture planning and implementation for complex SoCs, ensuring high testability.

Develop and validate DFT vectors for ATPG, memory BIST, and scan compression techniques.

Perform fault simulation and coverage analysis to identify and resolve testability gaps.

Collaborate with design and verification teams to integrate DFT structures into the design flow.

Create and maintain DFT-related documentation, including test plans and specifications.

Debug and resolve DFT-related issues during silicon bring-up and production testing.

Evaluate and implement new DFT methodologies and tools to improve test quality and efficiency.

Support post-silicon validation and failure analysis efforts related to DFT.

Developing and executing comprehensive verification plans to ensure DFT architecture meets specifications.

Creating efficient test patterns for fault detection and diagnosis in integrated circuits.

Performing fault simulations to validate the effectiveness of DFT structures and test patterns.

Implementing Automatic Test Pattern Generation (ATPG) flows for various fault models.

Designing and implementing Built-In Self-Test (BIST) solutions for embedded memories.

Inserting scan chains into digital designs to improve testability and fault coverage.

Implementing JTAG (IEEE 1149.1) interfaces for boundary scan testing and system-level debugging.

Planning and defining the overall DFT architecture for complex SoCs (Systems on Chip).

Analyzing test coverage metrics to identify areas for improvement and optimize test strategies.

Debugging and resolving issues related to failed test patterns during silicon validation.

Collaborating with design, verification, and physical design teams to integrate DFT features.

Creating and maintaining detailed documentation for DFT architectures, flows, and test procedures.