Develop comprehensive physical verification plans, outlining strategies and methodologies for verifying complex integrated circuit designs.

Execute physical verification flows using industry-standard EDA tools (e.g., Cadence, Mentor Graphics) to identify layout violations.

Perform layout versus schematic (LVS) checks to ensure the layout accurately reflects the intended circuit schematic.

Conduct design rule checking (DRC) to identify and resolve manufacturing-related layout violations.

Analyze and debug LVS and DRC violations, working closely with layout designers to implement necessary corrections.

Perform electrical rule checking (ERC) to identify potential electrical issues in the layout.

Collaborate with circuit designers to understand design intent and address any discrepancies found during verification.

Optimize physical designs for performance, power, and area, ensuring they meet specified requirements.

Create and maintain physical verification scripts and automation flows to improve efficiency and accuracy.

Document physical verification results and generate reports for design teams and management.

Stay updated with the latest physical verification methodologies, tools, and industry standards.

Participate in design reviews to provide feedback on physical design aspects and identify potential issues early in the design cycle.