Physical Verification Engineer

Functional Skills

Functional Skills are essential skills that help individuals perform tasks effectively in everyday life, work, and education.

Semiconductor Device Physics

Circuit Analysis

Static Timing Analysis (STA)

Physical Design Verification

Electromigration and IR Drop Analysis

Spice Simulation

Layout Design

Signal Integrity Analysis

Power Integrity Analysis

Design Rule Checking (DRC)

Layout Versus Schematic (LVS)

Process Technology

Soft Skills

Communication, teamwork, and critical thinking to ensure seamless project execution.

Attention to Detail

Problem-Solving

Communication

Analytical Thinking

Time Management

Teamwork and Collaboration

Adaptability

Critical Thinking

Technical Skills

Technical Skills are specialized abilities and knowledge needed to perform specific tasks or functions.

Semiconductor Device Physics

VLSI Design Flow

Physical Design Tools (e.g., Cadence, Synopsys)

Design Rule Checking (DRC)

Layout Versus Schematic (LVS)

Electrical Rule Checking (ERC)

Static Timing Analysis (STA)

Signal Integrity Analysis

Power Analysis and Optimization

Scripting (Python, TCL)

Knowledge of Semiconductor Manufacturing Processes

Problem-Solving and Debugging Skills

Version Control Systems (Git)

Knowledge of Foundries and Technology Nodes

Duties and Responsiblities

Task

95%

Develop comprehensive physical verification plans, outlining strategies and methodologies for verifying complex integrated circuit designs.

92%

Execute physical verification flows using industry-standard EDA tools (e.g., Cadence, Mentor Graphics) to identify layout violations.

90%

Perform layout versus schematic (LVS) checks to ensure the layout accurately reflects the intended circuit schematic.

88%

Conduct design rule checking (DRC) to identify and resolve manufacturing-related layout violations.

85%

Analyze and debug LVS and DRC violations, working closely with layout designers to implement necessary corrections.

82%

Perform electrical rule checking (ERC) to identify potential electrical issues in the layout.

80%

Collaborate with circuit designers to understand design intent and address any discrepancies found during verification.

78%

Optimize physical designs for performance, power, and area, ensuring they meet specified requirements.

75%

Create and maintain physical verification scripts and automation flows to improve efficiency and accuracy.

72%

Document physical verification results and generate reports for design teams and management.

70%

Stay updated with the latest physical verification methodologies, tools, and industry standards.

68%

Participate in design reviews to provide feedback on physical design aspects and identify potential issues early in the design cycle.

Work Activities

95%

Developing comprehensive verification plans and strategies for hardware designs.

92%

Creating robust and reusable testbenches using SystemVerilog and UVM.

90%

Running simulations to verify design functionality and identify bugs.

88%

Analyzing code and functional coverage to ensure thorough verification.

85%

Documenting and reporting bugs found during verification.

82%

Managing and maintaining regression suites for continuous verification.

80%

Using formal methods to prove design correctness.

78%

Configuring and using emulation platforms for hardware verification.

75%

Analyzing power consumption during verification.

72%

Evaluating design performance through verification.

70%

Reviewing RTL code for potential issues.

68%

Automating verification tasks using scripting languages.

Detailed Work Profile

Interests